Media Summary: Dr. Vivienne Sze is an associate professor in the EECS department at MIT. Vivienne is recognized for her leading work on ... In this video, our research work is presented: “RAMAN: Resource- Abstract: As the silicon technology approaches the Post-Moore's Law Era,

Efficient Algorithm Hardware Co Design - Detailed Analysis & Overview

Dr. Vivienne Sze is an associate professor in the EECS department at MIT. Vivienne is recognized for her leading work on ... In this video, our research work is presented: “RAMAN: Resource- Abstract: As the silicon technology approaches the Post-Moore's Law Era, Presentation at edge ai + vision alliance: ... Talk Title: Acceleration of bioinformatics workloads through Webinar Archive – Now Available! In this webinar, Prof. Priyadarshini (Priya) Panda, from the Intelligent Computing Lab at Yale ...

This is the recording of my invited online talk at the Washington DC Quantum Computing Meetup on June 7, 2026. Talk title: ... This talk is part of the Scientific Machine Learning Research Talks (SMaRT) Seminar Series, a joint initiative between Johns ... Keynote by Prof. Deming Chen, UIUC (VAST Lab Alumni) at ROAD4NN Workshop. Originally posted at ... More accurate machine-learning requires larger models – but large models pose problems both in the training and inference ...

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Ep 13: Energy-efficient Algorithm-hardware Co-design with Dr. Vivienne Sze, MIT
RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm–Hardware Co-desigN
Efficient Algorithm-Hardware Co-Design Methodology for Quantized LLM Acceleration
Once-for-All DNNs: Simplifying Design of Efficient Models for Diverse Hardware, [Invited Talk]
Can Alkan - Acceleration of bioinformatics workloads through hardware/algorithm co-design
Biologically Inspired Algorithm & Hardware Co-Design | Prof. Priya Panda (Yale University)
HiPEAC 2026 keynote 3: AI and hardware co-design: Taming quality, productivity, and reliability
Machine Learning for Reliable Quantum Computing: An Algorithm–Hardware Co-Design Perspective
Software-Hardware Codesign for Efficient In-Memory Regular Pattern Matching
Bio-Inspired Algorithm & Hardware Co-Design for Efficient AI | Dr. Priya Panda | JHU-IITD SMaRT
Elegant and Effective Co-design of Machine-Learning Algorithms and Hardware Accelerators  (ROAD4NN)
DAC Paper Review: Algorithm/Hardware Co-Design for In-Memory Computing with Minimal Circuit Overhead
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Ep 13: Energy-efficient Algorithm-hardware Co-design with Dr. Vivienne Sze, MIT

Ep 13: Energy-efficient Algorithm-hardware Co-design with Dr. Vivienne Sze, MIT

Dr. Vivienne Sze is an associate professor in the EECS department at MIT. Vivienne is recognized for her leading work on ...

RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm–Hardware Co-desigN

RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm–Hardware Co-desigN

In this video, our research work is presented: “RAMAN: Resource-

Efficient Algorithm-Hardware Co-Design Methodology for Quantized LLM Acceleration

Efficient Algorithm-Hardware Co-Design Methodology for Quantized LLM Acceleration

Abstract: As the silicon technology approaches the Post-Moore's Law Era,

Once-for-All DNNs: Simplifying Design of Efficient Models for Diverse Hardware, [Invited Talk]

Once-for-All DNNs: Simplifying Design of Efficient Models for Diverse Hardware, [Invited Talk]

Presentation at edge ai + vision alliance: ...

Can Alkan - Acceleration of bioinformatics workloads through hardware/algorithm co-design

Can Alkan - Acceleration of bioinformatics workloads through hardware/algorithm co-design

Talk Title: Acceleration of bioinformatics workloads through

Biologically Inspired Algorithm & Hardware Co-Design | Prof. Priya Panda (Yale University)

Biologically Inspired Algorithm & Hardware Co-Design | Prof. Priya Panda (Yale University)

Webinar Archive – Now Available! In this webinar, Prof. Priyadarshini (Priya) Panda, from the Intelligent Computing Lab at Yale ...

HiPEAC 2026 keynote 3: AI and hardware co-design: Taming quality, productivity, and reliability

HiPEAC 2026 keynote 3: AI and hardware co-design: Taming quality, productivity, and reliability

Further information: 'AI and

Machine Learning for Reliable Quantum Computing: An Algorithm–Hardware Co-Design Perspective

Machine Learning for Reliable Quantum Computing: An Algorithm–Hardware Co-Design Perspective

This is the recording of my invited online talk at the Washington DC Quantum Computing Meetup on June 7, 2026. Talk title: ...

Software-Hardware Codesign for Efficient In-Memory Regular Pattern Matching

Software-Hardware Codesign for Efficient In-Memory Regular Pattern Matching

https://pldi22.sigplan.org/details/pldi-2022-pldi/31/Software-

Bio-Inspired Algorithm & Hardware Co-Design for Efficient AI | Dr. Priya Panda | JHU-IITD SMaRT

Bio-Inspired Algorithm & Hardware Co-Design for Efficient AI | Dr. Priya Panda | JHU-IITD SMaRT

This talk is part of the Scientific Machine Learning Research Talks (SMaRT) Seminar Series, a joint initiative between Johns ...

Elegant and Effective Co-design of Machine-Learning Algorithms and Hardware Accelerators  (ROAD4NN)

Elegant and Effective Co-design of Machine-Learning Algorithms and Hardware Accelerators (ROAD4NN)

Keynote by Prof. Deming Chen, UIUC (VAST Lab Alumni) at ROAD4NN Workshop. Originally posted at ...

DAC Paper Review: Algorithm/Hardware Co-Design for In-Memory Computing with Minimal Circuit Overhead

DAC Paper Review: Algorithm/Hardware Co-Design for In-Memory Computing with Minimal Circuit Overhead

My review of the paper presented at DAC:

HiPEAC22 Keynote 1: Efficient Machine Learning: Algorithms-Hardware Co-design – Hai 'Helen' Li

HiPEAC22 Keynote 1: Efficient Machine Learning: Algorithms-Hardware Co-design – Hai 'Helen' Li

More accurate machine-learning requires larger models – but large models pose problems both in the training and inference ...